OpenLane is an automated RTL to GDSII flow based on several components i...
Deep learning toolkit-enabled VLSI placement
IP Core Library - Published and maintained by the Chair for VLSI Design,...
A High-performance Timing Analysis Tool for VLSI Systems
A modern and open-source cross-platform software for chips reverse engin...
Open source software for chip reverse engineering.
Gain an understanding of the fundamentals of Very Large-Scale Integratio...
Standard Cell Library based Memory Compiler using FF/Latch cells
The next generation of OpenLane, rewritten from scratch with a modular a...
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
ACT hardware description language and core tools.
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and...
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Faul...
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
VLSI EDA Global Router