Haskell to VHDL/Verilog/SystemVerilog compiler
OpenROAD's unified application implementing an RTL-to-GDS Flow. Document...
SERV - The SErial RISC-V CPU
A small, light weight, RISC CPU soft core
OpenLane is an automated RTL to GDSII flow based on several components i...
PlatformIO IDE for VSCode: The next generation integrated development en...
XLS: Accelerated HW Synthesis
Package manager and build abstraction tool for FPGA/ASIC development
The Ultra-Low Power RISC-V Core
A repository of gate-level simulators and tools for the original Game Boy.
RISC-V CPU Core (RV32IM)
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Hardware Description Languages
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
:seedling: Open source ecosystem for open FPGA boards