A collection of phase locked loop (PLL) related projects
A wishbone controlled scope for FPGA's
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. J...
Facilitates building open source tools for working with hardware descrip...
Virtio implementation in SystemVerilog
A bare bones, basic, ZipCPU system designed for both testing and quick i...
Wishbone controlled I2C controllers
Virtual development board for HDL design
CMod-S6 SoC
:deciduous_tree: A series of RISC-V soft core processor written from scr...
Quasar 2.0: Chisel equivalent of SweRV-EL2