opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
RISC-V CPU Core (RV32IM)
A self-hosting and educational C optimizing compiler
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Compact and Efficient RISC-V RV32I[MAFC] emulator
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus...
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
Small Processing Unit 32: A compact RV32I CPU written in Verilog
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice...