An abstraction library for interfacing EDA tools
A dual clock asynchronous FIFO written in verilog, tested with Icarus Ve...
XCrypto: a cryptographic ISE for RISC-V
SHA256 in (System-) Verilog / Open Source FPGA Miner
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. J...
Quickstart guide on Icarus Verilog.