A High-performance Timing Analysis Tool for VLSI Systems
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
A flexible framework for analyzing and transforming FPGA netlists. Offic...
A Standalone Structural Verilog Parser
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Faul...
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
VLSI EDA Global Router
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SP...