Open-source high-performance RISC-V processor
Chisel: A Modern Hardware Design Language
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom R...
Provides dot visualizations of chisel/firrtl circuits
:deciduous_tree: The next generation integrated development environment ...
Yet another toy CPU.
vector multiplication adder accelerator (using chisel 3 and RocketChip R...
Documentation for YatCPU
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Chisel Things for OFDM
Quasar 2.0: Chisel equivalent of SweRV-EL2