The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Expiremental Speech Recognition System using VHDL & MATLAB.
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric...
A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
Simple SoC in VHDL with full toolchain and custom board.