Scala based HDL
Latch
and LatchWhen
by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/944
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.8.0
This hotfix chery pick a few things from dev :
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.7.3a
The main purpose of this release is to fix a bug affecting the generation of tristate signals.
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.2...v1.7.3
Mostly, this fix a crash when generating blackbox in verilog with one file per component enabled
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.1...v1.7.2
synopsys_sim.setup
and other environment setup support by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/747
always
after states by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/765
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.0...v1.7.1
v1.7.0
Two new main features :
And many other additions and fixes !
Auto generated change log from github :
>>
operator by @Jeff-Ciesielski in https://github.com/SpinalHDL/SpinalHDL/pull/637
check
method to Stream. by @losfair in https://github.com/SpinalHDL/SpinalHDL/pull/673
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.6.4...v1.7.0
v1.6.4
Mostly 3 fixes :
In bulk :
V1.6.2
Mostly fixes with a some additions
Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.6.1...v1.6.2
Mostly fixes and small feature additions
v1.6.0
This version has 3 main things :
It also fix the Axi.incr issues with verilator, the ethernet cross clock domain and a few other things.