SpinalHDL Versions Save

Scala based HDL

v1.8.0

1 year ago

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.8.0

v1.7.3a

1 year ago

This hotfix chery pick a few things from dev :

  • 365f57ac Fix Verilator backend rtlIncludeDirs on windows
  • 9d20166c mergeRTLSource can now override the input safely #851 Dolu1990 09/20/2022 10:37 AM
  • 56400992 fix #863 Add allowOutOfRangeLiterals(my4bits === 42) to skip error. Also add SpinalConfig(allowOutOfRangeLiterals = true) to apply it everywhere

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.7.3a

v1.7.3

1 year ago

The main purpose of this release is to fix a bug affecting the generation of tristate signals.

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.2...v1.7.3

v1.7.2

1 year ago

Mostly, this fix a crash when generating blackbox in verilog with one file per component enabled

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.1...v1.7.2

v1.7.1

1 year ago

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.0...v1.7.1

v1.7.0

2 years ago

v1.7.0

Two new main features :

  1. Formal verification is now in a good state
  1. AFix floating point added (experimental, subject to changes)
  • Unifie unsigned/signed handeling
  • Tracking the exact range of possible values

And many other additions and fixes !

Auto generated change log from github :

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.6.4...v1.7.0

v1.6.4

2 years ago

v1.6.4

Mostly 3 fixes :

  • Nameable.composite now handle the ref owner properly
  • Fix cross clock pop reset for active low restets
  • Emited VHDL now check for bit access being out of range

In bulk :

  • Add Bool.asSInt(bitCount)
  • Vhdl package now check against out of bound
  • improve component definition name overlap error report
  • Add SEL handling to WishboneSlaveFactory
  • Fix asyncAssertSyncDeassertCreateCd reset polarity
  • add more test configs for the StreamFifoCcTester
  • #609 add SpinalReport.printZeroWidth()
  • #608 add Stream.forkSerial
  • Fix #610 (removePruned=true removing too much)
  • Add Axilite4 plic/clint
  • Add support for verilog simple dual port read first
  • add Any.ifMap(cond)(T => T)
  • improve the axi4ram design by pipeline stream
  • use show ahead pattern instead of plain logic.
  • use queue to break down the bStream and writeStream.
  • Verilog backend can now emit mux's switch with single target without using begin end
  • Add mssing code (Nameable.setPartialName with owner)
  • Add wishbone plic/clint
  • Add AxiLite4SpecRenamer for read only
  • Area vallCallbackRec is now able to properly override ref owner

v1.6.2

2 years ago

V1.6.2

Mostly fixes with a some additions

  • Verilog backend now implement a better randboot
  • add OHMasking.roundRobinMaskedInvert
  • LatencyAnalysis now assert no null arguements
  • Component postInitCallback now enforce the clockdomain
  • MemReadPort.bypass added
  • Regif merged
  • Fix SpiXdrMasterCtrl definition name being forced
  • Fix generation of RTS and CTS pins for UartCtrl
  • SwitchStatement.normalizeInputs fixed for scala 2.13.7+
  • SpiXdrMasterCtrl can now be used for more than 8 bits SPI frame and mixed width configurations
  • Fix non trivial verilog fixed signal are emited by using function (fix sim)
  • StateMachine build can now be manualy enforced
  • Fix Scope property push when never set by the past and no default
  • Fix a few ScopeProperty restore/rework
  • add more option to axi4 unburstify.
  • support useSize = false to axi4 unburstify.
  • Verilator backend no more copy rom bin files to the current directory.
  • Add downsizer for Axi4
  • JtagInstructionWrapper.ignoreWidth added to handle jtag chain (openocd updated too)
  • Component stub clock/reset removed bug fix
  • Backends do not check anymore the definition name uniquness of blackboxes (#546)
  • Add reset function to Axi4 related simulation agents.
  • Add more Symplify api
  • Add OhMux
  • Binary system utils added
  • Add globalCache(key, factory)
  • Fix scala 2.13 Apb3Decoder Seq
  • Fix #553 Verilog /* xx */ for CD BOOT kind
  • spinal.lib add Repeat(Data, times)
  • Axi4SlaveFactory now buffer the write responses to avoid some combinatorial link between streams
  • spinal.lib now implicitly add withBufferedResetFrom function to ClockDomain
  • add BitVector orMask/andMask

What's Changed

New Contributors

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.6.1...v1.6.2

v1.6.1

2 years ago

Mostly fixes and small feature additions

  • Mem with only 1 entry (translated into register) now allow multiple write ports (allow override)
  • add OHMasking.roundRobinMaskedFull
  • add OHMasking.roundRobinMasked
  • StateFsm now give name to the inner states
  • add axi4 bus support to Axi4ReadOnlyMonitor.
  • Add AreaRoot
  • Add checks to ensure the memory and its ports are correct hearchicaly speaking
  • Fix BmbToAxi4Bridge
  • add ScopePropertyContext with mutable and immutable map for better scaling
  • Add BufferCC.defaultDepth scopeProperty
  • Add support for write byte enable in BusSlaveFactory.writeMemWordAligned
  • added BUFGCE (bufg with clock enable) to clocking blackboxes for xilinx
  • Add lib.logic to infer decoding logic from some Masked specification
  • MuxOh now check that inputs have the same length
  • Better Reserved name not free reporting
  • BitVector.subdivide now have a strict option for non multiple bit lenght
  • Add AreaObject
  • Add StreamTransactionExtender.
  • Add setIdle and setBlocked functions to the axi buses,
  • spinal.lib now add Seq.groupByLinked
  • Fix AxiLite4 responses getters
  • MemWrite fix data width check
  • Add Module alias to Component in spinal.core
  • Prevent enum's mux normalizeInputs being applied to the selection exception
  • Add read/write instructionCtrl to JtagTap that allows for different Input/output data
  • add Growable.addRet(value)
  • add Mem.readAsyncPort
  • unassigned register with init will now emit a error on the first elaboration
  • add TraversableOnce.distinctLinked
  • ValCallbackRec can now name LinkedHashSet
  • add Data.wrapNext
  • Add Data.freeze() to error on any future assigment
  • add log2up(Int)
  • PhaseMemBlackboxing now implement wrapConsumers and removeMem
  • Add ScopeStatement.on(body)
  • Fix ClockDomain.apply
  • Can now apply tags to ClockDomain
  • Add ClassName object
  • Add ScopeProperty(defaultValue) construction
  • Add Mem.fill API
  • always emit timescale in verilog
  • fix #520 640x480#60 hz vga timings
  • deprecated BitVector.range, replaced by bitsRange
  • add BitVector.valueRange
  • StreamFifoLowLatency can now use Vec based storage
  • SpinalSim iverilog can now use includes
  • SpinalSim now try to figure out if a exception came for the hardware elaboration API
  • support inline rtl for BlackBox
  • Move lib.generator.Lock to core.fiber
  • Add xilinx s7 ff blackbox
  • Add MuxOH.or
  • Axi4Crossbar fix addPipelining being applied twice for nodes which are both master and slave at the same time
  • Remove Axi4Decoder low latency support
  • Fix Axi4 write decoders when used in low latency mode
  • Axi4 now handle better the absence of burst signal and id signl
  • Revert Verilog backend Mem.read multi symbole ram changes (no more xxxx[y : z]) to help inferation
  • Fix jtagTap bypass (thanks sebastien-riou)
  • UsbDeviceCtrlTester do not try isochronus on EP0 anymore
  • Add OhMasking.firstV2
  • Component.propagateIo removed (in favor of Data.toIo)
  • verilog reduction operators now handle zero width signals
  • Fix empty MultiData comparison
  • StateMachine whenIsActive now implement priorities.
  • States implementing the StateCompletionTrait should use whenIsActive with priority 1 to ensure they are called last.
  • StateMachine.bootAsEntry renamed into makeInstantEntry
  • Added some size check to Apb3Decoder
  • Merge branch 'SpinalHDL:dev' into dev
  • Add Bool ? T otherwise T
  • add cache for verilator binaries
  • SpinalSimConfig.compile do not mutate the config anymore
  • Fix ClockDomainResetGenerator.powerOnReset default value
  • Add support to give name to Option[Nameable]

v1.6.0

2 years ago

v1.6.0

This version has 3 main things :

  1. It fix some clockdomain crossing issues in the StreamCcByToggle and FlowCcByToggle.
  2. It add Scala 2.13 support
  3. Because of the scala 2.13 support and the preparation for scala 3 support, it has to drop some syntax. Now if you want do define a Bool signal, you need to write Bool() / in Bool() / out Bool()

It also fix the Axi.incr issues with verilator, the ethernet cross clock domain and a few other things.