RISC-V Assembly Language Programming
Change the number of bits in Figure 2.3 from 7 to 8 in order to show that 3-4=255.
The second addend in figure 2.8 showed the incorrect encoding for 1 (It showed a 9.)
This version adds and cleans up some of the examples in the sections on fixed and floating point number formats.
This is a minimal release suitable for reference when writing a disassembler for NIU CSCI 463.
I added some diagrams showing how the immediate values are decoded, removed some unfinished messy parts, and added a second page to the reference card at the end with links to descriptions of the various immediate value decoding diagrams & short discussions on how each instruction works.
I added some 'fix me' notes about the lack of clarity in the discussion of signed & unsigned overflow. Of course, the RISC-V has no overflow flags. So this material is background for the some-day discussion on determining overflow in those cases when it is of interest (which is outlined in 'The RISC-V Instruction Set Manual, Volume I')